The present invention relates generally to semiconductor fabrication, and more particularly to a dual damascene process used in semiconductor fabrication.
In the field of semiconductor fabrication, a pathway, hole, or other passage through a substrate of an integrated circuit is known as a xe2x80x9cviaxe2x80x9d. The via can be filled with an electrically conductive material, such as a metal, so that electrical current can flow to or from a metal line, i.e., a metal contact, that is embedded in the substrate at an end of the via.
During the formation of an integrated circuit, transistor devices are fabricated on semiconductor material, such as silicon. A dielectric layer is deposited over the transistor devices. Conductive plugs extend from the bottom surface to the top surface of the dielectric layer, enabling electrical contact with the transistors to be achieved through the dielectric layer. A film having a low dielectric constant K is then deposited over the dielectric layer. Metal lines extend from the bottom surface to the top surface of the low K film, enabling electrical contact with the conductive plugs and the transistors to be achieved through the low K film. Thus, the metal lines can be used to electrically connect the outside world to the transistors within the integrated circuit.
The low K film with the metal lines embedded therein is further covered with an insulating layer of electrically nonconductive material. Thus, the metal line is disposed below the upper surface of the integrated circuit. By forming a via through the nonconductve material and filling the via with conductive material, it is possible to make an electrical connection to the metal line at different vertical levels, thereby allowing access to the metal line from outside of the integrated circuit. Such arrangements are used to provide external contacts for integrated circuits.
In the lithography process of semiconductor fabrication, an attempt is made to create the via in a location that is aligned with the underlying metal line so that electrical communication can be established between the metal line and an electrically conductive material that will fill the via. In order to make the alignment easier, it is known to provide the metal line with an area of increased width, known as a xe2x80x9clanding padxe2x80x9d, through which the metal line makes electrical contact with the conductive material inside the via. FIG. 1 illustrates a metal line 20 having such a landing pad 22 of increased width W. The landing pad 22 is aligned with a via 24.
In order to minimize circuit size and maximize transistor density, the widths of metal lines and vias have been reduced in succeeding generations of devices. However, the extra widths required by the above-described landing pads limit the achievable increase in circuit density. For this reason, the excess width accorded to landing pads have been all but eliminated, or at least reduced to less than one nanometer. Such structures, wherein the width of the landing pad is substantially equal to the width of the connected via, are known as xe2x80x9cborderless structuresxe2x80x9d, or xe2x80x9cborderless viasxe2x80x9d.
The elimination of the extra width of the landing pad makes alignment of the via to the metal line difficult in such borderless vias. During the lithography process, the alignment of the via to the underlying metal line cannot be controlled to less than about ten nanometers misalignment due to inherent tool and processing issues. FIG. 2 illustrates the results of an inadvertent misalignment between a via 24 and an underlying metal line 26, resulting in the via 24 being partially disposed outside the borders of the metal line 26.
FIGS. 3a-3e illustrate the steps of an exemplary dual damascene process in which inadvertent misalignment between a via and a metal line occurs. In dual damascene processing, a thin layer 28 (FIG. 3a) of a material having a low dielectric constant K, such as silicon oxide (SiO), is disposed on a semiconductor wafer (not shown). The thickness of the silicon oxide layer 28 can be approximately between 0.5 and 1.0 micrometer. A trench or channel is etched in the silicon oxide layer 28, and a diffusion barrier layer 30 of tanium/tanium nitride (Ta/TaN) is disposed on the silicon oxide layer 28. A layer 32 of copper (Cu) is disposed on the barrier layer 30 by electrical plating such that the trench in the oxide layer 28 is filled with copper, and the whole surface of the wafer is covered with copper. The barrier layer 30 prevents the copper from diffusing into the oxide layer 28.
FIG. 3b illustrates the results of a chemical mechanical planarization (CMP) process that removes the copper layer 32 and the barrier layer 30 until the top surface of the oxide layer 28 is reached. The remaining copper layer 32 forms a metal line 33. An etch stop barrier layer 34 (FIG. 3c) of silicon carbide (SiC) is then disposed on the wafer such that the etch stop barrier layer 34 is substantially planar. The etch stop barrier layer 34 can alternatively be composed of SiOxCyNz, wherein It is possible for any one or two of x, y and z to be zero. That is, the etch stop barrier layer 34 can be composed of SiOxCyNz, SiOxCy, SiOxNz, SiCyNz, SiOx, SiCy, or SiNz.
Next, an intermetal dielectric (IMD) layer 36 (FIG. 3d) of a material having a low dielectric constant K, such as SiOxCyHz, SiOF, SiOx, or carbon based film, is disposed over the entire surface of the wafer. The etch stop barrier layer 34 prevents diffusion of the copper from the metal line 33 into the IMD layer 36.
As illustrated in FIG. 3e, a plug hole is plasma etched in the IMD layer 36 in order to form a via 38. Due to machine limitations, the via 38 has been inadvertently misaligned with the metal line 33, as often occurs. The rate of vertical progression of the etch process is slower through the etch stop barrier layer 34 than through the IMD layer 36 because the etch process is designed and optimized for the material composition of the IMD layer 36. The etch stop barrier layer 34 is over-etched to ensure that all of the etch stop barrier layer 34 is removed from the top surface of the copper metal line 33, thereby allowing the copper to make good electrical contact with the conductive material to be inserted into the via 38.
After the etch stop barrier layer 34 has been etched through, the over-etching results in etching of the oxide layer 28 due to the poor selectivity between the etch stop barrier layer 34 and the oxide layer 28. The etching of the oxide layer 28 results in the formation of a microtrench 40 along the edge of the barrier layer 30. The rate of etch is faster through the oxide layer 28 than through the etch stop barrier layer 34, which tends to result in increasing the depth of the microtrench 40.
The formation of a microtrench 40 is undesirable because it is difficult for chemicals to penetrate into the microtrench 40. Thus, it is difficult to remove polymer from the microtrench 40 during a solvent cleaning process. It is also difficult to subsequently remove any solvent chemicals that manage to penetrate into the microtrench 40. Trapped solvent may corrode the metal line 33. Another problem associated with microtrenching is that the diffusion barrier layer 30 can be etched away from the side of the metal line 33 during the etching process, thereby reducing the reliability of the device. Yet another problem is that a microtrench provides a possible avenue for conductive bridging between adjacent metal lines.
One approach to solving the problems associated with microtrenching is to change the parameters of the etch process, such as gas flows, pressure, temperature and power, in order to improving the selectivity of the etch between the etch stop barrier layer 34 and the oxide layer 28. However, it has been found that it is difficult to achieve an acceptable level of selectivity because the oxide layer 28 has very weak resistance to the plasma etching.
What is needed in the art is a method of reducing microtrenching during the creation of borderless vias in a dual damascene process.
The present invention provides a method of increasing the effective thickness of the etch barrier layer in the areas where microtrenching could otherwise occur. Thus, the etch process is slowed down and inhibited from penetrating through the etch barrier layer in these areas of potential microtrenching.
In accordance with one embodiment of the present invention, there is provided a method of making a semiconductor device, including providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. An upper surface of the second element slopes downwardly toward the upper surface of the first element. A first layer of a second substantially nonelectrically conductive material is disposed over the upper surface of the first element and the upper surface of the second element. An etching process is performed such that the layer is perforated above the upper surface of the first element and imperforated above the downwardly sloping upper surface of the second element.
In accordance with another embodiment of the present invention, there is provided a method of making a semiconductor device, including providing a first element formed of a first substantially electrically conductive material. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. A first layer of a second substantially non-electrically conductive material is disposed on the first element and the second element. The layer has a thickness relative to a predetermined direction. The thickness is greater along a junction between the first element and the second element than along the first element. An etching process is performed in the predetermined direction such that the layer is perforated along the first element and imperforated along the junction between the first element and the second element.
In accordance with yet another embodiment of the present invention, a semiconductor device is created by providing a first element formed of a first substantially electrically conductive material. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. A first layer of a second substantially nonelectrically conductive material is disposed on the first element and the second element. The layer has a thickness relative to a predetermined direction. The thickness is greater along a junction between the first element and the second element than along the first element. An etching process is performed in the predetermined direction such that the layer is perforated along the first element and imperforated along the junction between the first element and the second element.
An advantage of the present invention is that microtrenching is avoided, thereby reducing the occurrence of bridging between metal lines and increasing device reliability and chip yield.
Another advantage is that the interconnect delay or response time of the device is reduced.
Yet another advantage is that improved lithography tolerances with respect to alignment can be tolerated.
A further advantage is that the etch barrier layer can be over-etched without resulting in microtrenching.
The above and other features and advantages of the present invention will become apparent from the following description and the attached drawings.